This application claims priority to Korean Patent Application No. 2004-6981, filed on Feb. 3, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to image sensors, and more particularly to a correlated double sampling (CDS) amplifier for a complementary metal oxide semiconductor (CMOS) image sensor for improving signal to noise (S/N) ratio.
2. Description of the Related Art
A complementary metal oxide semiconductor (CMOS) image sensor (CIS) has a number of advantages over a charge-coupled device (CCD), including low driving voltage, low power consumption, fabrication from a standard CMOS process, and high integration. Therefore, the CIS is likely to replace the CCD in the future.
However, unlike the CCD, the CIS requires a high-resolution analog-to-digital converter (ADC) for converting an analog signal received from an active pixel sensor (APS) to a digital signal.
Conversion of an analog signal to a digital signal is carried out using a single ADC or column ADCs. In the case of the former, analog signals received from APSs of all columns are converted within a predetermined time to digital signals by a single ADC driven at high speed. Therefore, the chip area of the ADC is minimized. However, since the ADC is driven at high speed, power consumption of the CIS disadvantageously increases. On the other hand, in the case of the latter, simple structural ADCs are arranged in a column-wise fashion and consume less power but have increased chip area.
For high performance, the signal to noise ratio (S/N ratio) of the CIS is desired to be maximized. In this respect, almost all CISs use a correlated double sampling (CDS) method. In the CDS method, a reset voltage and a signal voltage are generated from a pixel of the APS array, and a difference between the reset voltage and the signal voltage indicates the intensity of light sensed by the pixel. With such a CDS method, the CIS removes fixed pattern noise or low frequency noise, thereby improving the S/N ratio. Here, the “reset voltage” indicates a voltage generated by the APS during reset sampling and the “signal voltage” indicates a voltage generated by the APS during signal sampling.
The ADC converting an analog signal from the CDS method to a digital signal also determines the S/N ratio of the CIS. For example, a range of the analog signal converted by the ADC is desired to be higher for enhanced S/N ratio of the CIS.